1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a method for forming active regions of a semiconductor device.
2. Description of the Related Art
As devices are highly integrated, a line width of a pattern becomes narrower. Due to technical limitations of exposure equipment, patterning with the use of conventional photoresist layer may be difficult.
To overcome the limitation, a Double Patterning Technology (DPT) process may be used. Particularly, a Spacer Patterning Technology (SPT) process using spacers may be used.
In addition, when patterns are to be formed in both cell regions and peripheral regions, such as an isolation layer, simultaneously forming patterns in both cell regions and peripheral regions according to the SPT process may be difficult. Therefore, patterns are formed in the cell regions first, and subsequently, a single mask process is additionally performed in the peripheral regions.
Therefore, the number of steps in a manufacturing process is increased and exposure equipment has to be additionally used. These features decrease margin and makes the patterning difficult. Furthermore, even after the final patterns are formed, the patterns may lean during a subsequent cleaning process due to the delicacy of the patterns.